15 min read Beginner Lesson 08 (of 30)
Course 01 · Part 2 — Digital Logic & Circuits

Lesson 08 — How the CPU Works: From Instruction to Execution

Discover how a processor pulls binary instruction codes from memory and executes calculations one after another through real hardware architecture.

Brief Introduction

When you enter 5 + 3 into a calculator, the answer seems obvious: 8.

Yet to the CPU, "5 + 3" is not an abstract human thought—it is a sequence of encoded instructions, binary operands, and electronic micro-operations.

Our journey: Program → Memory → Instruction → Fetch → Decode → Execute → Result

1. What Is the CPU and What Does It Do?

The CPU (Central Processing Unit) is the primary computational brain of the computer, responsible for interpreting and executing software instructions:

Arithmetic (+, -, *, /)
Logical (AND, OR, XOR)
Data Movement (Load/Store)
Comparisons (>, <, ==)
Control Flow (Branch, Jump)
Memory Coordination

2. Programs, Instructions, and Machine Code

While programs reside permanently on non-volatile SSD storage, execution transfers them through memory stages up to the processor registers:

SSD / Storage RAM Cache (L1/L2/L3) CPU Registers

CPUs do not execute Python or Java source code directly. Compilers translate high-level language statements into native machine instructions (ISA: x86-64 or ARM).

3. The Program Counter (PC)

How does the CPU know where the next instruction lives in memory? It tracks execution using a dedicated register named the Program Counter (PC):

Address 100 → Instruction A (Currently executing)
Program Counter = 104 (Address of next instruction)

4. The Classic Instruction Cycle: Fetch → Decode → Execute

1. Fetch

The CPU uses the PC address to fetch the instruction from cache/RAM and loads it into the Instruction Register (IR).

2. Decode

The Control Unit decodes the binary opcode: identifying what operation to run and which operand registers are involved.

3. Execute

The ALU or target execution engine performs the requested computation and writes the result to destination registers.

5. Concrete Walkthrough: Executing 5 + 3

1. Fetch & Decode: ADD R1, R2, R3
2. Read Operands: Register R1 = 5, Register R2 = 3
3. ALU Execution: Binary Adder outputs 5 + 3 = 8
4. Writeback: Store result into Destination Register R3 = 8

6. The Control Unit — The Traffic Police

The ALU can compute, but it cannot decide on its own when to add or when to subtract. The Control Unit generates the control signals that synchronize data flow across the entire processor.

7. Pipelining — Accelerating Modern Processors

A modern CPU does not idle waiting for an instruction to finish all stages. Like an industrial assembly line, it overlaps stages across consecutive instructions:

Inst 1: [ Fetch ] → [ Decode ] → [ Execute ]
Inst 2: ───→ [ Fetch ] → [ Decode ] → [ Execute ]
Inst 3: ─────────→ [ Fetch ] → [ Decode ] → [ Execute ]

8. Branching, Loops, and Function Calls

When an if/else condition or while loop executes, branch instructions update the Program Counter to jump forward or backward to target memory addresses.

9. The Internal Architecture of the CPU

Central Processing Unit (CPU)
Program Counter (PC)
↓
Instruction Register (IR) & Control Unit
↓ Control Signals ↓
Registers (R1, R2, R3...) ⇄ ALU
↕ Data Bus / Memory ↕
RAM / Cache Memory

🧠 Key Takeaways

  1. The CPU is the central processing engine that executes program instructions.
  2. The Program Counter (PC) tracks the memory address of the next instruction.
  3. Fetch → Decode → Execute defines the universal instruction execution loop.
  4. The Control Unit orchestrates timings and signals across all internal units.
  5. Registers and the ALU work in concert to deliver lightning-fast computation.
  6. Pipelining overlaps execution phases to achieve higher instruction throughput per clock cycle.
🚀 Next Lesson

Lesson 09 — How Data Moves Inside a Computer: Bus Architecture

In the next lesson, we examine:

Data Bus Address Bus Control Bus Memory Addressing Motherboard

And understand how the CPU, RAM, and motherboard interconnects communicate at immense bandwidths.