How Memory is Addressed: RAM, Virtual Memory & Pointers

Memory: An Infinite Array of Addressable Bytes

From low-level pointer arithmetic in C to the multi-level page tables of modern operating systems, memory addressing is the fundamental mechanism linking algorithms to physical DRAM.

1–6. Memory Addresses & Byte-Addressability

RAM is structured as an indexed linear sequence of storage cells:

Address vs Data

An Address specifies where data is located (e.g., location 1002).
The Data specifies what value is stored there (e.g., value 99).

Byte-Addressable Architecture

Modern computers do not assign unique addresses to individual bits; instead, every contiguous 8-bit block (1 byte) possesses its own distinct integer address.

7–12. Pointers, Arrays & Pointer Arithmetic

In programming, a Pointer is simply a variable that stores the memory address of another variable rather than a direct raw value.

Pointers and Array Memory Layout in C:

int numbers[4] = {10, 20, 30, 40};
int *p = numbers; // p holds base address 1000

Address 1000 ──► [ 10 ] (*p)
Address 1004 ──► [ 20 ] (*(p + 1)) // advances 4 bytes
Address 1008 ──► [ 30 ] (*(p + 2))
Address 1012 ──► [ 40 ] (*(p + 3))

Because array elements are stored contiguously in memory, CPU caches maximize their Spatial Locality, fetching the entire block in a single transfer.

13–16. Virtual Memory vs Physical Memory

User-space applications never touch physical DRAM directly. Instead, every program operates in an isolated, private Virtual Address Space.

Process A (Chrome)

Virtual address 0x1000 is mapped to physical RAM frame 0x5000.

Process B (VS Code)

The exact same virtual address 0x1000 is safely mapped to completely distinct physical frame 0x9000.

17–24. Pages, Page Tables and the MMU Translator

Virtual memory is divided into fixed-size blocks called Pages (typically 4 KiB). Physical RAM is divided into matching chunks called Frames.

How the MMU Translates Addresses:

Virtual Address: [ Virtual Page Number (VPN) | 12-bit Page Offset ]
│
MMU looks up Page Table
│
Physical Address: [ Physical Frame Number (PFN) | 12-bit Page Offset ]

The Page Offset remains unchanged; only the virtual page number is swapped for the matching physical frame number.

25–27. TLB (Translation Lookaside Buffer): Ultra-Fast Translation Cache

Looking up multi-level page tables in RAM for every single memory access would cut processor speed in half. The CPU houses the TLB—a specialized on-chip associative cache holding recent translations.

Virtual Address ──► [ TLB Hit? ] ──(Yes: 1-cycle Physical Address)──► RAM
└──(No: TLB Miss ──► Page Table Walk ──► Update TLB)

28–32. Memory Protection and Stack vs Heap

Stack

Fast, automatic memory managed by the CPU stack pointer. Stores function call frames, parameters, local variables, and return addresses. Deallocated automatically when functions return.

Heap

Dynamically allocated memory requested by programs at runtime (malloc / new). Persists until explicitly freed or reclaimed by a garbage collector.

34–36. Page Faults and Demand Paging

When a program requests a virtual page that is not currently resident in physical RAM (often swapped out to SSD storage), the CPU triggers a Page Fault interrupt. The operating system kernel transparently loads the 4 KiB page from disk into a free RAM frame and resumes the instruction without application interruption.

46–50. Master Memory Abstraction & Execution Model

PROGRAMMER CODE (*p = 42) │ ▼ VIRTUAL MEMORY ADDRESS │ TLB Cache Check (Fast Path) │ ┌────────────┴────────────┐ ▼ ▼ TLB Hit TLB Miss │ │ │ Page Table Walk in MMU │ │ └────────────┬────────────┘ ▼ PHYSICAL RAM ADDRESS │ L1 / L2 / L3 CPU Cache Check │ ▼ DRAM SILICON CELLS (Capacitors) │ ▼ TRANSISTORS & VOLTAGE

🧠 Key Takeaways

Memory Address: A unique numerical identifier for each byte-sized memory cell in a byte-addressable system.
Pointer: A variable that stores the physical or virtual memory address of another value rather than the value itself.
Virtual Memory: Grants every process its own isolated memory address space, ensuring complete process security and preventing memory interference.
Pages & Frames: Memory is grouped into standard 4 KiB units; Page Tables maintain the mappings between virtual pages and physical frames.
MMU & TLB: Dedicated hardware translates virtual addresses to physical RAM addresses in a single cycle using the TLB cache.
Stack vs Heap: Function-scoped automatic memory (Stack) versus programmer-allocated persistent memory (Heap).

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Lesson 21 — Clock, Timing & CPU Synchronization: How Computers Stay in Sync

Discover quartz crystal oscillators, clock signals, what 3 GHz actually means, and how billions of transistors synchronize in perfect cadence.

How Memory Is Addressed: RAM, Memory Addresses, Virtual Memory & Pointers