20 min read Intermediate Lesson 19 of 29
Part 4 — Processor & Microarchitecture

What Is Actually Inside a CPU? Modern Processor Architecture

Although a modern processor looks like a single tiny silicon chip from the outside, inside it houses billions of transistors structured into an ultra-fast computational factory. Where is data stored, where are calculations performed, how does the CPU predict upcoming instructions, and how does it execute billions of instructions per second?

The Silicon Symphony: Billions of Calculations Every Nanosecond

A single CPU core can execute several billion instructions per second, synchronizing billions of transistors in fractions of a nanosecond.

Discover the intricate pipeline, prediction engines, execution units, and multi-level caches that make modern computation possible.

1–3. CPU Core: A Self-Contained Execution Engine

Modern processors contain multiple independent Cores. Each core acts as an autonomous execution factory:

Fundamental Building Blocks Inside a CPU Core:
Control Logic Instruction decode & control
Registers Fastest storage on chip
Execution Units ALU, FPU, SIMD
L1/L2 Cache Hierarchical memory buffers

4–8. Deep-Dive into CPU Registers

General-Purpose Registers (GPR)

In x86-64, registers such as RAX, RBX, RCX, RDX, R8–R15 hold intermediate operands and computational variables with sub-nanosecond access.

Program Counter (PC / RIP)

Holds the memory address of the next instruction to fetch from memory or instruction cache.

Stack Pointer (SP / RSP)

Tracks the top of the call stack, managing function call frames, local variables, and return addresses.

Status Flags (EFLAGS / RFLAGS)

Indicates arithmetic results and processor state: Zero Flag (ZF), Carry Flag (CF), Sign Flag (SF), and Overflow Flag (OF).

9–12. Types of Execution Units: ALU, FPU & SIMD

🔢 Integer ALU

Executes whole-number additions, subtractions, multiplications, bitwise AND/OR/XOR operations, and bit shifts.

📐 Floating-Point (FPU)

Dedicated silicon hardware for high-precision decimal math (such as 3.14159 × 2.71828) following IEEE 754 standards.

⚡ Vector / SIMD

Single Instruction Multiple Data: Applies a single operation simultaneously across 4 to 16 numbers in a vector register (e.g., AVX-512, ARM NEON).

15–22. CPU Cache Hierarchy & Locality

While a CPU core can perform calculations in ~0.3 nanoseconds, retrieving data from main RAM takes 50–80 nanoseconds. To eliminate this colossal latency gap, processors incorporate a 3-tier cache hierarchy:

L1 Cache (~32-64 KB) ~1 nanosecond (per-core dedicated)
L2 Cache (~1-2 MB) 3–5 nanoseconds (per-core)
L3 Cache (~16-96 MB) 10–15 nanoseconds (shared across cores)

Temporal Locality: Recently accessed memory addresses are highly likely to be accessed again soon.
Spatial Locality: When an address is read, the CPU pre-loads the surrounding 64-byte block (Cache Line) anticipating upcoming access.

23–26. Instruction Pipelining: The Assembly Line

Cycle 1: [Fetch Inst 1] Cycle 2: [Decode Inst 1] [Fetch Inst 2] Cycle 3: [Execute Inst 1] [Decode Inst 2] [Fetch Inst 3] Cycle 4: [Memory Inst 1] [Execute Inst 2] [Decode Inst 3] [Fetch Inst 4] Cycle 5: [Writeback 1] [Memory Inst 2] [Execute Inst 3] [Decode Inst 4]

Rather than waiting for an instruction to finish entirely before starting the next, each clock cycle advances every stage forward, multiplying throughput dramatically.

27–29. Branch Prediction & Out-of-Order Execution

Branch Prediction

When encountering an if/else branch, the CPU does not stall waiting for the condition; it predicts the outcome using historical patterns and executes instructions speculatively.

Out-of-Order Execution (OoO)

If an instruction is stalled waiting for memory from RAM, the CPU continues executing downstream independent instructions, later retiring them in strictly correct program order.

38–44. ISA vs Microarchitecture & Performance Metrics

The ISA (Instruction Set Architecture) is the contract between software and hardware (e.g., x86-64, ARM64, RISC-V). The Microarchitecture is the internal engineering implementation in silicon.

CPU Performance = (Instruction Count) × (CPI: Cycles Per Instruction) × (Clock Cycle Time)

45–48. Master Modern CPU Core Architecture

INSTRUCTION FETCH & L1 I-CACHE │ Branch Predictor & PC Register │ ▼ DECODE & MICRO-OP QUEUE │ Register Rename & Reorder Buffer │ ▼ RESERVATION STATIONS / SCHEDULER ┌───────────────────────────┼───────────────────────────┐ ▼ ▼ ▼ INTEGER ALUs FLOATING POINT (FPU) LOAD/STORE UNITS (Math & Logic) (Vector / SIMD Math) (L1 Data Cache / RAM) │ │ │ └───────────────────────────┼───────────────────────────┘ ▼ IN-ORDER RETIREMENT & REGISTERS

🧠 Key Takeaways

  • CPU Core: An autonomous silicon execution engine equipped with its own control logic, registers, and private caches.
  • Registers: The fastest storage on the chip—PC tracks the next instruction to fetch, while SP maintains the active stack frame.
  • Execution Units: Discrete functional units—ALU for integers, FPU for decimals, and SIMD for parallel vector calculations.
  • Cache Hierarchy: Overcomes the RAM latency bottleneck using L1, L2, and L3 caches exploiting temporal and spatial locality.
  • Pipelining & OoO: Instructions overlap in an assembly line and independent instructions execute out-of-order to maximize throughput.
  • Clock speed alone does not determine performance; Instructions Per Cycle (IPC) is equally vital.
🚀 Next Lesson

Lesson 20 — How Memory Is Addressed: RAM, Virtual Memory & Pointers

Learn how CPUs locate specific bytes among billions, how virtual memory provides total process isolation, and how pointers operate in memory.